In an integrated semiconductor memory, for example, a DRAM (=Dynamic Random Access Memory) semiconductor memory, the memory cells are arranged in one or more memory cell arrays. An individual DRAM memory cell, which comprises a selection transistor and a storage capacitor, is connected to a bit line for reading in and reading out information. When the DRAM memory cell is activated for a read or write access, the selection transistor of the memory cell is turned on by a corresponding control signal on a word line. The storage capacitor of the DRAM memory cell is connected to the bit line via the turned-on path of the selection transistor. During a read-out operation, the charge stored on the storage capacitor alters the voltage potential of the bit line. If the storage capacitor is charged to a high voltage potential corresponding to a logic 1 state, for example, then a potential increase occurs during the read-out of the memory cell on the bit line. If the electrodes of the storage capacitor are charged to a low voltage potential corresponding to the logic 0 state, for example, then a potential decrease occurs during a read-out operation on the bit line. However, the quantity of charge present on the electrodes of the storage capacitor generally effects only a small potential fluctuation on the bit line. The bit line is therefore connected to a sense amplifier via a controllable switch when an item of information is being read into the memory cell or from the memory cell. When an item of information is read out, the sense amplifier amplifies a potential increase on the bit line to form a high voltage potential on the output side, whereas it converts a potential decrease into a low voltage potential on the output side.
When an item of information is written to the memory cell, the sense amplifier charges the storage capacitor of the relevant memory cell to the high voltage potential if a logic 1 information item is intended to be stored, and to the low voltage potential if a logic 0 information item is intended to be stored.
Since the storage capacitor can store the charge stored on its electrodes only over a very limited time, the charge is refreshed in a refresh operation. For this purpose, the memory cell is read internally from time to time. If the sense amplifier detects a potential increase on the bit line during this internal read-out operation, then it drives the bit line connected to the memory cell with a high voltage level. If the sense amplifier detects a potential decrease on the bit line, then it drives the bit line connected to the memory cell with the low voltage level. This ensures that a high or low charge level is always present on the electrodes of the storage capacitor.
In order to illustrate an integrated semiconductor memory constructed in this way, FIG. 6 illustrates a sense amplifier 100, which can drive a first memory cell array on its left-hand side via a bit line BLl and a complementary bit line /BLl with respect thereto and a second memory cell array on its right-hand side via a bit line BLr and a complementary bit line /BLr with respect thereto. On its left-hand side, an internal signal line BSA and a complementary signal line /BSA with respect thereto of the sense amplifier 100 are connected for this purpose, via a switching unit 50l to the bit line BLl and, respectively, the complementary bit line /BLl with respect thereto of the first memory cell array. In the event of an access to the second memory cell array on its right-hand side, the internal signal line BSA and the complementary signal line /BSA with respect thereto of the sense amplifier 100 can be connected via a switching unit 50r to a bit line BLr and, respectively, a complementary bit line /BLr with respect thereto.
The sense amplifier 100 furthermore comprises a circuit unit 20 for amplifying a logic 1 information item, a circuit unit 30 for amplifying a logic 0 information item, and a circuit unit 40, by which the bit lines BLl and BLr and the complementary bit lines/BLl and /BLr can be connected to a local data line LDQ and, respectively, a complementary local data line /LDQ with respect thereto. The local data lines LDQ and /LDQ are generally connected to a secondary sense amplifier (not illustrated here).
The circuit unit 20 comprises the two switching transistors 21 and 22, which are designed as p-channel transistors, for example. The control terminal of the switching transistor 21 is connected to the complementary signal line /BSA of the sense amplifier and the control terminal of the switching transistor 22 is connected to the signal line BSA of the sense amplifier. The two switching transistors are connected to one another via their common terminal A20. The common terminal A20 is connected via a switching transistor TH, which can be controlled by a control signal PSET, to the terminal for applying a high voltage potential VBLH corresponding to the logic 1 information item. Furthermore, the terminal A20 is connected to the signal line BSA via the controllable path of the switching transistor 21 and to the complementary signal line /BSA of the sense amplifier via the controllable path of the switching transistor 22.
The circuit unit 30 comprises two switching transistors 31 and 32 designed as n-channel transistors. A control terminal of the switching transistor 31 is connected to the complementary signal line /BSA of the sense amplifier. A control terminal of the switching transistor 32 is connected to the signal line BSA of the sense amplifier. The two switching transistors 31 and 32 are connected to one another via a common terminal A30. The terminal A30 is connected via a switching transistor TL, which can be controlled by a control signal NSET, to a terminal for applying a low voltage potential VBLL corresponding to the logic 0 information item. The terminal A30 is connected to the signal line BSA via the controllable path of the switching transistor 31 and to the signal line /BSA via the controllable path of the switching transistor 32.
The circuit unit 40 comprises the two switching transistors 41 and 42, which are designed as n-channel transistors, for example. The two switching transistors can be controlled by a control signal CSL applied to a common control terminal CIN. The signal line BSA of the sense amplifier 100 is connected to the local data line LDQ via the controllable path of the switching transistor 41. The complementary signal line /BSA of the sense amplifier 100 is connected to the complementary local data line /LDQ via the controllable path of the switching transistor 42.
The signal line BSA and the complementary signal line /BSA of the sense amplifier are connected via the switching unit 50l to the bit line BLl and, respectively, the complementary bit line /BLl with respect thereto for driving a memory cell SZ in the first memory cell array. For this purpose, the switching unit 50l comprises a switching transistor 51l and a switching transistor 52l, which are designed as n-channel transistors, for example. The two switching transistors can be controlled via a common control terminal MINl for applying a control signal MUXl. The signal line BSA and the complementary signal line /BSA with respect thereto of the sense amplifier 100 are connected via the switching unit 50r to the bit line BLr and, respectively, the complementary bit line /BLr with respect thereto for driving a memory cell in the right-hand memory cell array. The switching unit 50r comprises the switching transistor 51r, via the controllable path of which the signal line BSA of the sense amplifier can be connected to the bit line BLr, and a switching transistor 52r, via the controllable path of which the complementary signal line /BSA can be connected to the complementary bit line /BLr. The two switching transistors can be controlled via a common control terminal MINr for applying a control signal MUXr.
A circuit unit 10 for precharging the bit lines to a common precharge potential is connected between the bit line BLl and the complementary bit line /BLl of the first memory cell array and the bit line BLr and the complementary bit line /BLr of the second memory cell array. The circuit units 10 in the first and second memory cell arrays for this purpose comprise a switching transistor 11, via which the bit lines BLl and BLr can be connected to their complementary bit lines /BLl and /BLr. The bit lines BLl and BLr are furthermore connected via a switching transistor 12 and a current limiter transistor TB, which is driven by a control signal VINT, to a terminal VEINl and, respectively, a terminal VEINr for applying a precharge voltage VBLEQ. The complementary bit lines /BLl and /BLr are connected via a switching transistor 13 and the current limiter transistor TB to the terminal VEINl and VEINr, respectively, for applying the precharge potential VBLEQ.
For reasons of clarity, a memory cell SZ is connected only to the bit line BLl of the first memory cell array and a storage capacitor SC′ is connected to the complementary bit line /BLl with respect thereto of the first memory cell array. The memory cell SZ is designed as a DRAM memory cell and comprises a selection transistor AT, via the controllable path of which a storage capacitor SC is connected to the bit line BLl. The selection transistor AT can be controlled by applying a control signal WL to its control terminal WIN.
Operation of the sense amplifier 100 and the circuit components connected thereto is described below. For reading an item of information into the memory cell or from the memory cell, the sense amplifier 100 is switched into a first operating state. The selection transistor AT is turned on, as a result of the memory cell SZ being driven with the control signal WL. The storage capacitor SC is connected to the bit line BLl via the controllable path of the selection transistor. In the first operating state of the sense amplifier 100, the switching transistors 11, 12 and 13 of the circuit unit 10 of the first memory cell array are turned off by the applying a control signal EQL to their common control terminal EINl. The two switching transistors 51l and 52l are turned on by applying a corresponding state of the control signal MUXl. The bit line BLl and the complementary bit /BLl are connected via the turned-on paths of the switching transistors 51l and 52l to the signal line BSA and, respectively, the complementary signal line /BSA of the sense amplifier 100. At the same time, the two switching transistors 51r and 52r are turned off by applying a corresponding state of the control signal MUXr to the control terminal MINr, so that the signal line BSA and the complementary signal /BSA of the sense amplifier 100 are disconnected from the bit lines BLr and the complementary bit line /BLr of the second memory cell array. The two switching transistors TL and TH are turned on by the control signal NSET and PSET, respectively, so that the high voltage potential VBLH is present at the common terminal A20 of the two p-channel switching transistors 21 and 22 and the low voltage potential VBLL is present at the common terminal A30 of the two switching transistors 31 and 32.
If it is assumed that the bit lines and complementary bit lines are charged to the precharge potential VBLEQ before a read access, then the potential increase relative to the precharge potential VBLEQ, as described above, occurs during the read-out of an information item that is stored in the memory cell SZ on the bit line BLl. The potential increase is transmitted onto the signal line BSA of the sense amplifier via the switching transistor 51l. The potential increase on the signal line BSA causes the switching transistor 32 to be turned on. In this case, the low voltage potential VBLL is present on the complementary signal line /BSA and is transmitted onto the complementary bit line /BLl via the turned-on switching transistor 52l. The storage capacitor SC′ is thereby charged to the low voltage potential VBLL. As a result of the low voltage level VBLL on the complementary signal line /BSA of the sense amplifier 100, the switching transistor 31 is turned off, whereas the switching transistor 21 is turned on. The high voltage level VBLH arises on the signal line BSA via the turned-on p-channel transistor 21, and in turn reliably turns off the switching transistor 22. In this switching configuration, a high voltage potential VBLH corresponding to the logic 1 information item is written back to the memory cell SZ (refresh operation). In order to read out the information stored in the memory cell SZ, the switching transistors 41 and 42 are additionally turned on by the driving with a corresponding state of the control signal CSL, so that the signal line BSA is connected to the local data line LDQ and the complementary signal line /BSA is connected to the complementary data line /LDQ.
If a logic 0 information item was stored in the memory cell SZ, then a potential decrease relative to the precharge potential VBLEQ occurs on the bit line BLl upon activation of the selection transistor AT. The potential decrease of the bit line BLl is transmitted onto the signal line BSA of the sense amplifier 100 via the turned-on switching transistor 51l. The potential decrease on the signal line BSA causes the p-channel switching transistor 22 to be turned on. As a result, the high voltage level VBLH arises on the complementary signal line /BSA. As a result, the switching transistor 21 is reliably turned off and the switching transistor 31 is turned on. The low voltage level VBLL arises on the signal line BSA via the turned-on switching transistor 31, and in turn reliably turns off the switching transistor 32. In this switching configuration of the sense amplifier 100, the low voltage level VBLL corresponding to the logic 0 information item is written back to the memory cell SZ (refresh operation). The storage capacitor SC′ connected to the complementary bit line /BLl is charged to the high voltage level VBLH, by contrast. If the logic 0 information item is intended to be read from the memory cell SZ, then the two switching transistors 41 and 42 are turned on by the driving with a corresponding state of the signal CSL, so that the signal line BSA is connected to the local data line LDQ and the complementary signal line /BSA is connected to the complementary data line /LDQ.
If an item of information is intended to be read into or from a memory cell of the second memory cell array on the right-hand side of the sense amplifier 100, then the switching transistors 51l and 52l are turned off. The switching transistors 51r and 52r are turned on by the driving with a corresponding state of the control signal MUXr, so that, in this case, the bit lines BLr and /BLr are connected to the signal lines BSA and /BSA of the sense amplifier 100. The switching transistors 11, 12 and 13 of the circuit unit 10 of the second memory cell array are turned off. The functioning of the sense amplifier 100 and its circuit components 20, 30 and 40 otherwise corresponds to the function described in the event of an access to the first memory cell array.
Between a read and write access to a memory cell, the sense amplifier is operated in a second operating state. In the second operating state of the sense amplifier, the bit lines are charged to the common precharge potential VBLEQ. For this purpose, the respective switching transistors 11, 12 and 13 of the circuit units 10 of the first and second memory cell arrays are turned on by the driving with a corresponding state of the control signal EQL and EQLr, respectively. The bit lines BLl and BLr are connected to the precharge potential VBLEQ via the respective current limiter transistors TB and the respectively turned-on switching transistors 12. Furthermore, the complementary bit lines /BLl and /BLr are likewise connected to the precharge potential VBLEQ via the respectively turned-on switching transistors 13 and the respective current limiter transistors TB. The bit lines and their complementary bit lines are connected to one another in each case via the turned-on switching transistors 11.
It is know that in a sense amplifier constructed in this way and connected via switching transistors to a bit line pair of a left-hand and right-hand memory cell array, the switching transistors are used to increase the total capacitance of a complementary bit line of a bit line pair during a read operation. This makes it possible to reduce the parasitic capacitive coupling between bit lines of a bit line pair during the read operation.
There are numerous disadvantages associated with a sense amplifier of this type. Although the switching transistors 51 and 52, which are generally designed as n-channel transistors and connect the signal line BSA and the complementary signal line /BSA of the sense amplifier 100 to the bit lines BL and the complementary bit lines /BL, respectively, are turned on in the first operating state of the sense amplifier, the switching transistors 51, 52 still represent a resistance. An increase in the channel resistance of the switching transistors occurs when the integrated semiconductor memory is operated in a low temperature range, since the threshold voltage of the switching transistors increases at low temperatures. A signal, for example, the voltage signal VBLH corresponding to the logic 1 information item, which passes via one of these transistors, is thus attenuated. With the use of n-channel transistors, problems occur when transmitting high voltage levels from the bit line BL onto the signal line.
In order to improve the current yield, the switching transistors are therefore driven with high control voltages for the purpose of turning them on. Such control voltages are in the region of 2.9 V, for example. In order to prevent the gate contact from being destroyed by these control voltages, the oxide layer below the gate contact is made very thick. The transistors used are therefore generally thick-oxide transistors.
In order to further increase the current yield of the switching transistors connected between the bit lines of the memory cell arrays and the signal lines of the sense amplifiers, transistors with large width and length ratios are used. However, fabrication of switching transistors with thick oxide layers and large channel widths requires a large amount of space in the circuit layout.
Besides increasing the channel widths, attempts have been made to increase the width and length ratio by reducing the channel lengths of the switching transistors. However, transistors with short channel lengths exhibit large fluctuations in the threshold voltage. Process fluctuations in the dimensioning of the channel length are therefore accompanied by large fluctuations in the threshold voltage.